An efficient FFT architecture for OFDM communication systems

The FFT (Fast Fourier Transform) processor plays a critical part in speed and power consumption of the Orthogonal Frequency Division Multiplexing (OFDM) communication system. This paper presents a high level implementation of a high performance FFT for OFDM Modulator and Demodulator. The design has been coded in VHDL and targeted into Xilinx Virtex-E XCV3200E FPGAs. The hardware requirement comparison shows that our implementation outperforms other implementations of FFT on the same series of FPGAs. Radix-2² algorithm has the same multiplicative complexity as the radix-4 algorithm, but retains the butterfly structure of radix-2 algorithm. The design is parameterizable in terms of input word length, output word length, twiddle factor word length, and processing word length. Also, it is scalable in terms of number of stages.