FPGA-based Implementation of a Real-Time Distance Evaluation Algorithm for Wireless Localization Systems

The work introduces the FPGA implementation of a novel high-precision TDOA distance evaluation system based on a OFDM symbol that is completely charaterized, generated, and processed in the digital domain. The system exploits a Software-Defined Radio architeture, thus its charateristics can be adjusted by means of simple software modifications performed on the FPGA. The system was implemented using the FPGA (Cyclone IV-E EP4CE115F29C8L) available through the Altera's DE2-115 development board. The FPGA implementation comprises a digital hardware, that extracts the distance by processing the incoming signal in both the time and frequency domains, and a NIOS processor to transmit the elaborated data to a main central micro-controller unit (MCU). The implementation requires about 120k bits of memory and 44k logic elements (of which about 30k are registers).