A systematic design approach for nanoscale inductor-less regulated cascode stages

This paper presents a framework for the systematic design of inductor-less regulated cascode (RGC) stages. Targeting high-speed fiber optic data receiver front-ends, the technique reported combines the symbolic solution of the small-signal model of the RGC and the use of g_m/I_D based lookup tables to efficiently explore and optimize the resulting design space. A practical design is discussed and implemented in a 180 nm six-metal-layer CMOS process with 1.8V supply. The accuracy and viability of the proposed approach is validated through circuit simulation.