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A systematic design approach for nanoscale inductor-less regulated cascode stages

  • C. Talarico
    ,
  • G. D'Amato
    ,
  • G. Avitabile
    ,
  • G. Piccinni
    ,
  • G. Coviello
Research Output:
Chapter in Book/Report/Conference proceeding
Conference contribution

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Abstract

This paper presents a framework for the systematic design of inductor-less regulated cascode (RGC) stages. Targeting high-speed fiber optic data receiver front-ends, the technique reported combines the symbolic solution of the small-signal model of the RGC and the use of gm/ID based lookup tables to efficiently explore and optimize the resulting design space. A practical design is discussed and implemented in a 180 nm six-metal-layer CMOS process with 1.8V supply. The accuracy and viability of the proposed approach is validated through circuit simulation.

Publication metrics

PlumX, opens in new tab

Citations
3
Captures
5

Access to documents

Bibliographic Information

Output type

Research Output:
Chapter in Book/Report/Conference proceeding
Conference contribution

Host publication Subtitle

29th Symposium on Integrated Circuits and Systems Design: Chip on the Mountains

Original language

English

Article number

7724057

Publication milestones

  • Published - 27/10/2016

Publication status

Published - 27/10/2016

Publisher

Institute of Electrical and Electronics Engineers Inc.

Publication series

  • Publication series name: Proceedings - SBCCI 2016: 29th Symposium on Integrated Circuits and Systems Design: Chip on the Mountains
    Volume: 2016-August

ISBN (Electronic)

9781509027361

Publication IDs

  • Scopus: 85039908598

Host publication title

Proceedings - SBCCI 2016