A novel optimization framework for the design of gilbert cell mixers

This paper presents a new framework for the design optimization of a CMOS down-conversion mixer based on a conventional double balanced Gilbert cell. The framework exploits the g_m/I_D methodology to find the transistors' dimensions that optimize the tradeoff between conversion gain, noise figure, third-order intercept and power DC consumption of the mixer. The mixer has been designed using a 0.13 μm process from IHP Microelectronics, and it exhibits a conversion gain of 13.1 dB at 0 dBm local oscillator's power. The average noise figure is 11.9 dB, the input third-order intercept is -2.8 dBm and the output third-order intercept is 9.7 dBm. Finally, the chip-core without bonding pads measures only 0.028 mm by 0.031 mm and it dissipates 1.5 mW with a 1.5 V supply.